Jugraj Singh

ADC Assignment 2

4 min read

This capacitor array is often used in ADCs and DACs and is used for building a signal on that is controlled by toggling the switches from ground to a reference voltage:

The voltage is sampled on the top plates of the capacitors at .

Capacitor values:


etc.

Initially:

Input signal:

with

The sampling switch is implemented by NMOS transistor with the following parameters:

Threshold voltage:

Current factor for a square transistor :

Dimensions:

Oxide capacitance density:

Gate-drain overlap capacitance:

Use the strong-inversion square-law transistor equation.

Questions

A

Calculate the SNR after sampling.

To calculate the SNR we use the SNR formula where for we model after noise. For we have that , the RMS is then .
The total capacitance then is . Then the is given by the thermal noise formula, so .
So the SNR in dB is

B

The capacitor is implemented as a series connection of two capacitors of value .

How does the SNR change?

Since the two series capacitors will equal the single capacitor value, according to , the value calculated for the thermal noise will not be influenced. So I expect the SNR to not change.

However, there might still be slight parasitic effects that can cause some distortion.

C

After sampling, all switches are toggled to .

What is the SNR?

Since the thermal noise was calculated during the sampling phase, in the conversion the switching to should not affect the SNR.

D

A parasitic capacitance

is present from now on.

What is the SNR?

I assume this could make the SNR better, but will cause issues in concerns like matching and settling speed since it is capacitance introduced not by design. My motivation for the SNR going down comes from the earlier seen noise formula. Since the total capacitance is in the denominator, the noise would actually go down. I believe this is because the thermal energy can be distributed over a larger stored charge. is connected to the top plate and ground together with the other capacitors, so this will affect our noise. Our now is so our noise power now is .

So .

E

Due to a design error, the bottom-plate-to-ground switch of is missing.

What is the SNR after sampling?

What is the SNR when, after sampling without ground connection of , this bottom plate is connected to ?

Assume the capacitor was initially uncharged:

This means that the capacitor can not sample anymore, since it is always at 0. Our new sampling capacitance then is . Then our becomes

so our new SNR is

→ What happens after connected to VREF? Doesnt matter only for when sampling.

F

The sample switch is implemented with an NMOS transistor .

needs a drive voltage

What is the minimum voltage for ?

Vt = 0.2 so VGS = 0.4 Since Vs is Vin, highest Vin is 0.3 + VDC

G

What is in that case the pedestal step?

Make a drawing of for a full sampling cycle.

VON and Vin ⇒ channel charge half charge to C (assumption)

delta V on C dg ⇒ 3 fC. Qgate is -(VGate) amplification 1.02x

H

What is the settling time for:

  • the lowest signal level?
  • the highest signal level?

use R ON and fast is 20ps low is 100ps, RON,low * Chold for slow

I

Sketch the expected distortion (THD) from DC to maximum frequency.

  • HD2 - omega deltaRC / 4

J

Comparing the SNR and the THD, advise whether to:

  • increase
  • or decrease

Graph View